In data processing systems, data signals are input to a central processor from one or more sources. In such systems the transfer of data is synchronized with respect to a common clock referred to as a master clock. That is, the master clock is the timing reference for all processing operations, including input, manipulation and out-processing. The principal functional sections of the processor communicate with each other through signals that represent data, instructions and control signals. The order, timing and direction in which information flows within and between the functional sections of the processor are synchronized with the master clock. It will be appreciated that a direct failure of the master clock will interrupt the transfer and processing of data, and an indirect malfunction or invalid clock signal will cause loss of data or the transmission of invalid data.
The stability of the pulses produced by the master clock is critical when a flip-flop is used to transfer data. In such operations, there is a certain period of time during which the data signal must remain stable relative to the rising clock edge input to establish an accurately timed output. For instance, the data signal must have assumed a logic 1 value for a certain amount of time prior to the onset of the clock rising edge and must maintain the logic 1 value and not transition to a logic 0 for a certain period of time after the rising clock signal has achieved logic 1 value. The foregoing clock/data timing constraints must be observed to obtain valid data synchronization so that the output data signal is a faithful and accurate representation of the input data signal.